1. Field of the Invention
The present invention relates to a semiconductor memory, and particularly, to a technique of controlling the timing of activation of a sense amplifier of a random access memory (RAM) in a specific operation mode set according to an external instruction.
2. Description of the Related Art
RAMs presently marketed include standard RAMs that provide only a normal read/write function and dual port RAMS that provide, in addition to the normal read/write function, a collective write (a flash write) function and a write transfer function.
FIG. 4 shows essential part of the dual port RAM.
The RAM includes word lines WLs (only one is shown), pairs of complementary bit lines BL and BLX (only one pair is shown), a pair of flash write control signal lines FL and FLX, a write transfer control signal line TR, an I/O port DIN/DOUT on the RAM side, and an I/O port SDIN/SDOUT on the serial access memory (SAM) side.
A memory cell MC having a transistor Q and a capacitor C is formed at an intersection between the word line WL and the bit lines BL and BLX. N-channel transistors QW and QW' are formed at intersections between the signal lines FL and FLX and the bit lines BL and BLX. The transistors QWs and QW's are used when collectively writing data of 0 or 1 into the memory cells MCs.
N-channel transistors QL1 and QL2 are formed in the bit lines BL and BLX, respectively, and are connected in series. These transistors are turned ON and OFF in response to the potential of the signal line TR, to control data transfer between the memory cell MC on the RAM side and a cell MS on the SAM side.
A sense amplifier 30 senses and amplifies a voltage difference between the bit lines BL and BLX, in response to a sense amplifier activation signal SE.
Operation modes of the dual port RAM will be explained with reference to a signal timing chart of FIG. 5.
A normal mode (a normal read cycle) will now be explained. The word line WL is set to level HIGH to turn ON the cell transistor Q. The cell capacitor C then provides the bit line BL with cell data, to slightly increase the potential of the bit line BL. This produces a small voltage difference between the bit lines BL and BLX. After a period t1 in which the small voltage difference becomes stable, the sense amplifier activation signal SE is set to HIGH to activate the sense amplifier 30. The sense amplifier 30 then amplifies the small voltage difference to a given level.
A flash write mode will now be explained. Similar to the normal mode, the word line WL is set to HIGH to turn ON the cell transistor Q. The cell capacitor C then provides the bit line BL with cell data, to slightly increase the potential of the bit line BL. To forcibly set every memory cell in the RAM to 0 or 1, the signal line FL is increased to HIGH to turn ON every transistor QW. This results in dropping the potential of the bit line BL lower than the original level, to produce a small voltage difference between the bit lines BL and BLX. The profile of this voltage difference is opposite to that of the voltage difference in the normal mode. After a period t2, the activation signal SE is set to HIGH to activate the sense amplifier 30. The sense amplifier 30 amplifies the small voltage difference to a given level.
A write transfer mode will now be explained. This mode requires a period t3 from when the word line WL is increased to HIGH until a voltage difference between the bit lines BL and BLX becomes stable. In this mode, the voltage difference changes differently from the normal mode.
As explained above, a voltage difference between the bit lines differs from mode to mode. To secure a correct operation in each mode, the timing of activation of the sense amplifier 30 must be determined according to the mode that requires the longest stabilizing time for the voltage difference. Namely, the timing of a rise or a fall of the activation signal SE is fixed according to the mode accompanying the longest stabilizing time.
If a voltage difference between the bit lines in the flash write mode becomes stable slower than in the normal read mode, the timing of execution of the normal read will be delayed. This causes a waste of access time in the normal read mode.
If the timing of the normal read mode determined by the stabilizing time of the voltage difference is the slowest among the modes, the problem will not be conspicuous. In this case, however, an access time in the other modes that are faster than the normal read mode in stabilizing the voltage difference will cause a waste of access time.
In this way, the conventional semiconductor memory that fixes the timing of activation of a sense amplifier according to a worst operation mode having the slowest voltage difference stabilizing time causes a waste of access time in operation modes that stabilize a voltage difference faster than the worst mode. This hinders a high-speed memory operation.